Error Correction in Flash Memory Devices
Flash memory devices have been known for many years. NAND-type flash memories differ from other types of flash memories (e.g. NOR-type), among other characteristics, by the fact that a certain number of information bits, written to the memory, may be read from the memory in a “flipped” state (i.e. different from the state that the original bits were written to the memory).
In order to overcome this phenomenon and to make NAND-type memories usable by real applications, it is a common technique to use Error Correction Codes (ECC) in conjunction with these memories.
There is an ongoing need for improved techniques and apparatus for handling error correction in flash memory devices, and in storage devices that include memory other than flash memory.
A Discussion of Device Architecture
FIG. 1A (prior art) is a block diagram of a flash memory storage device 260 (prior art). The flash memory storage device includes a flash memory 270 and a flash controller 280 operative to read data and to write data to the flash memory 270. The terms “program”, “programming”, “programmed”, and “programmable” are used herein interchangeably with the terms “write”, “writing”, “written”, and “writable”, respectively, to denote the storing of data in a flash memory.
One example of a flash memory storage device is a “peripheral flash storage device.” Peripheral flash storage devices are well-known in the art of computing, in form factors such as USB flash drives (UFD); PC-cards; and small storage cards used with digital cameras, music players, handheld and palmtop computers, and cellular telephones.
FIG. 1B (prior art) is a block diagram of a peripheral flash memory storage device 260*(the asterisk indicates that the flash memory storage device is a peripheral flash storage device) that is “coupled with” or configured to exchange data with a host device 310 (for example, a laptop or desktop or handheld computers, digital camera, mobile telephone, music player, and video game consoles) via device-side interface 250. Peripheral flash memory storage device 260* and host device 310 communicate with each other via communications link 300 using host-side interface 350 and device-side interface 250 (for example, respective USB or SD interfaces).
In one example, flash memory storage device 260* provides data-reading and data-writing services to host device 310. Data received by flash memory storage device 260* from host device 310 is written to flash memory 270 by flash controller 280. Furthermore, in response to “data read” requests received by flash memory storage, flash controller 280 reads data from flash memory 270.
Errors may be corrected in the read data at “read time” or at any later time. The error-correction may be carried out at least in part by flash controller 280, at least in part by host device 310 (for example, by execution of executable code 340 in RAM 330 by host-side processor 320 or in any other manner), and any other location and in any other manner.
The skilled artisan will appreciate that “peripheral flash storage devices” are not the only class of flash memory storage devices. For example, certain mobile phones, desktop or laptop computers, PDA devices or other electronic devices may also include flash memory and a flash controller, and may not necessarily be configured to couple with a host device and/or provide data reading services and/or data writing service for a host device.
The skilled artisan will appreciate that the flash memory devices described in FIGS. 1A-1B are just one class of peripheral storage memory device, and other memory devices may include other types of volatile memory, such as magnetic memory (for example, magnetoresistive random-access memory (MRAM) or hard disk platters). Furthermore, it is appreciated that the some peripheral storage devices may use volatile memory instead of, or in addition to, flash memory 270.
Multi-Die Flash Devices
Although flash memory 270 is illustrated as a single unit in FIG. 1B, it is appreciated by the skilled artisan that flash memory 270 may reside on a single die or may reside on multiple dies. FIG. 2A (prior art) is a block diagram of a multi-die flash memory 270 that includes N flash dies, where N is a positive integer. On each flash die resides a plurality of flash memory cells (not shown in FIG. 2A).
It is appreciated that memory other than flash memory (for example, random-access memory (RAM) such as dynamic RAM (DRAM) or static RAM (SRAM)) may also be provided as multiple dies.
Flash Memory Cells and Flash Blocks
In flash memory devices, the indivisible unit of data storage is the flash memory “cell”. FIG. 2B (prior art) illustrates a cross-section of a typical prior-art electrically-erasable non-volatile memory cell 100 (NAND flash). A metal gate 181 is deposited over an insulating oxide layer 183 atop a semiconductor channel 185, thereby forming a metal-oxide-semiconductor field-effect transistor (MOSFET). During fabrication, a floating gate 187 is embedded entirely within oxide layer 183, such that floating gate 187 is completely insulated electrically from all conducting paths. Electrons deposited on floating gate 187 cannot normally drain off and therefore tend to remain in place. A suitable amount of electrical charge thus present on floating gate 187 creates a static electrical field which, because of the field effect, influences the charge carriers in semiconductor channel 185, thereby allowing the conductivity of semiconductor channel 185 to indicate the relative amount of charge on floating gate 185. Hence a suitable charge on floating gate 187 can serve as non-volatile data storage. For programming, charge is injected onto floating gate 187, and for erasing, charge is removed therefrom. Both of these operations are accomplished via quantum-mechanical processes such as the tunneling effect and the hot electron effect. Oxide layer 183 is extremely thin, so that in the presence of a suitably-high attractive electrical field the wave-function of an electron residing in semiconductor channel 185 can extend across oxide layer 183 and overlap floating gate 187. Under such conditions, there is a significant probability that an electron in semiconductor channel 185 will cross through oxide layer 183 and appear on floating gate 187. This phenomenon is exploited to program cell 100. In Single-Level Cell (“SLC”) flash memory, a cell stores only a single bit (data values of ‘0’ and ‘1’). In Multi-Level Cell (“MLC”) flash technology, a cell can store 2 bits by exhibiting 4 distinct voltage levels on floating gate 187 (data values of ‘00’, ‘01’, ‘10’, and ‘11’). More generally, a MLC cell can store n bits by exhibiting 2n distinct voltage levels on floating gate 187. Certain threshold values of the conductivity of semiconductor channel 185, corresponding to different amounts of charge on floating gate 187, are predetermined to unambiguously discriminate between different data values.
Reference is now made to FIG. 2C. Cells within a memory device are arranged in an array, usually having subdivisions. A number of cells are commonly configured into a “page” 110, which contains cell 100, along with similar cells 102 and 104, and so forth. Likewise, a number of pages are commonly configured into a “block” 120, which contains page 110, along with similar pages 112 and 114, and so forth. Finally, a number of blocks make up an entire device 130, which contains block 120, along with similar blocks 122 and 124, and so forth.
It is appreciated that memory other than flash memory (for example, random-access memory (RAM) such as dynamic RAM (DRAM) or static RAM (SRAM)) may also be organized into cells, pages and blocks.
Word Lines
Reference is now made to FIG. 2D (prior art) which illustrates an array 10 of cells 100. Cells 100 are accessed by word lines 103 connected to control gates of cells 100 and by bit lines 107 connected to array 10 at the drain side. Bit line 107 is selected by a bit line select (drain side) 109 and a bit line select (source side) 111. Typically, in some NAND flash devices, not all cells 100 have the same reliability. For example, cells that are closer to the bit line select (drain side) 109 are more sensitive to disturbance errors than other cells 105, while cells closer to the source side select 111 have better reliability characteristics.
It is appreciated that memory other than flash memory (for example, random-access memory (RAM) may also be accessible using word lines and bit lines.